Several detailed electrical specifications have been written for telephone transmission lines. One such specification is commonly referred to as the T1 specification originally developed by Bell Laboratories. The T1 specification provides for the transmission of digitally encoded signals at a 1.544 megabits per second bit rate.
The T1 specification requires that the digital pulses be of a certain amplitude and shape at a point on the transmission referred to as the digital cross connect. This specification requires that the output of a transmission line driver have a shape which is not a perfect square wave, but rather a square wave having overshoot on its rising edge and undershoot on its falling edge.
As transmitters were developed for the T1 specification, it became desirable to integrate the transmitter to the extend possible on a single integrated circuit chip without requiring the external reactive components previously used to form the proper overshoot and undershoot. One method of eliminating the discrete reactive components has been to digitally form the overshoot and undershoot by dividing the pulse into multiple segments. The first segment being the initial rise or overshoot voltage, another segment being the logical 1 voltage level of the pulse, another section being the undershoot voltage, and still another section being the logic 0 level or reference voltage level. In order to generate these four different voltage levels, a 2X or 4X clock must be generated by the transmitter and synchronized with the incoming clock from the digital data source. The present invention provides a circuit for generating either a 2X or 4X clock frequency in the transmitter.
Telephone transmission lines which use the T1 protocol develop jitter or noise-induced phase modification in the data channels. This jitter accumulates on the transmission channel and can cause loss of synchronization between the transmitter and receiver of a telephone transmission line thereby causing loss of data in the transmission line.
A method used in the past to attenuate this jitter has been to use a First-In, First-Out (FIFO) storage register. Data is clocked into the FIFO in synchronization with the incoming data, and the data is clocked out of the FIFO by an independent clock which is close to the incoming clock frequency. However, the two clocks won't be in synchronization, and some of the incoming data will be lost if the independent clock is slower, even by a small amount, than the data rate of the incoming data, or additional erroneous bits will be added to the data stream if the independent clock is faster, even by a small amount, than the incoming data bit rate. While this loss of data or insertion of data may be negligible when voice data is being sent over the data channel, if computer data is being transferred over the transmission system, then the deleted bits or additional bits may cause serious problems to users of the transmission system.
Therefore it can be appreciated that a clock multiplier/jitter attenuator circuit for a transmitter for a digital transmission line which provides a multiple of the transmission line clock frequency that is synchronized to the average frequency of the incoming data and which also attenuates jitter appearing on the incoming digital channel and which can be fabricated almost entirely on a single integrated circuit chip is highly desirable.